1. Field of the Invention
The present disclosure relates to a liquid crystal display device including a field programmable gate array (or “FPGA”) and a method for initializing the FPGA.
2. Discussion of the Related Art
An active matrix type liquid crystal display device (or “AMLCD”) represents video data using the thin film transistor (or “TFT”) as the switching element. As the AMLCD can be made in thin flat panel with lightening weight, nowadays in the display device market, it is replacing cathode ray tube (or “CRT”) and applied to portable information appliances, computer devices, office automation appliances, and/or television sets.
The AMLCD comprises a data driving circuit for supplying the data signals to the data lines of the LCD panel, a gate driving circuit for sequentially supplying the gate pulse (or scan pulse) to the gate lines of the LCD panel, and a timing controller for controlling the operating timing of the data driving circuit and the gate driving circuit.
Recently, in order to improve the video quality of the AMLCD, various algorithms are added to the timing controller for compensating or enhancing the video quality. These algorithms are typically applied as hardware methods. However, applying these algorithms with hardware type need much more manufacturing tact time and cost because more times and efforts are required to design, to pack, and to test the timing controller having newly applied algorithm.
For the application specific IC (or “ASIC”), it is impossible to re-set the setting of the ASIC after it is manufactured. Therefore, when it is required to apply new algorithms or to update the exist algorithms, the ASIC should be re-designed and re-manufactured with a lot of time for testing and cost.
The field programmable gate array, as one of the programmable logic device (or “PLD”), is the integrated circuit (or “IC”) which can be reset its logical circuit configuration, at any time. The FPGA includes the programmable logic elements and the programmable connections. The FPGA may further include a phase-locked loop (or “PLL”) for multiplying the frequency of the input clock.
The programmable logic elements include the logic elements such as the AND gate, the OR gate, the XOR gate, and NOT gate. By connecting these logic elements included in the FPGA, any complex circuit can be configured in the FPGA. By modifying the software for the logic connections of the logic elements, the function of the FPGA can be reset. The FPGA have been mainly used for developing various ASIC. Recently, the FPGA is applied to the mass production for the electric appliances.
The FPGA can be applied to a liquid crystal display device for sampling the data of the input video data and for compensating the pixel data according to the pre-set algorithms. In order to operate the FPGA in stable status, the FPGA should be initialized stably. When the FPGA and the built-in (embedded) PLL of the FPGA are initialized according to the power sequence of the LCD, the initialization of the PLL may be unstable, so that the FPGA may operate in the state that the output of the PLL is not locked. In that case, as the pixel data is not normally output from the FPGA, the LCD does not represents video data normally.